IC chip package with isolated vias
US7365421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jun 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC chip package includes a substrate (2), a chip (5), a plurality of bonding wires (52), and a cover (6). The substrate has a top surface, a receiving chamber (23) having an opening at the top surface, a plurality of solder pads (3) arranged around the top surface and respectively corresponding to the solder pads arranged at a bottom surface opposite to the top surface, and a plurality of vias (4) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads (51) arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate, and covers the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.