Speculative instruction issue in a simultaneously multithreaded processor
US7366877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2003 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Apr 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.