Low-latency synchronous-mode sync buffer circuitry having programmable margin
US7366943B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Aug 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The periodic sync signal, synchronous with the source clock, is used to output to an unload pointer counter in the target clock domain the deassertion of a reset signal prior to the nominal alignment of the source clock and the target clock for sampling on the nominally aligned target clock edge. The deassertion of the reset signal is output to a load pointer in the source clock domain coincident with the nominally-aligned edges of the source clock and the target clock. Both loading and unloading start based on the reset deassertion being sampled on the nominally aligned edges in the appropriate clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.