Jonathan Owen
30Patents
11h-index
39Co-inventors
75Inventor score
Filing activity: Aug 4, 2000 → Aug 28, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6950438B1 | System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system | Electricity | 82 | Expired |
| US6721813B2 | Computer system implementing a system and method for tracking the progress of posted write transactions | Physics | 61 | Expired |
| US6665742B2 | SYSTEM FOR RECONFIGURING A FIRST DEVICE AND/OR A SECOND DEVICE TO USE A MAXIMUM COMPATIBLE COMMUNICATION PARAMETERS BASED ON TRANSMITTING A COMMUNICATION TO THE FIRST AND SECOND DEVICES OF A POINT-TO-POINT LINK | Electricity | 34 | Expired |
| US6751684B2 | System and method of allocating bandwidth to a plurality of devices interconnected by a plurality of point-to-point communication links | Electricity | 32 | Expired |
| US6760838B2 | System and method of initializing and determining a bootstrap processor [BSP] in a fabric of a distributed multiprocessor computing system | Physics | 31 | Expired |
| US6745272B2 | System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system | Electricity | 30 | Expired |
| US7640315B1 | Implementing locks in a distributed processing system | Physics | 20 | Expired |
| US7069361B2 | System and method of maintaining coherency in a distributed communication system | Electricity | 19 | Expired |
| US7430622B1 | Extended fairness arbitration for chains of point-to -point devices having multiple virtual channels | Physics | 19 | Active |
| US7287105B1 | Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation | Electricity | 18 | Expired |
| US8412971B2 | Method and apparatus for cache control | Emerging Cross-Sectional Technologies | 12 | Active |
| US7870407B2 | Dynamic processor power management device and method thereof | Physics | 8 | Active |
| US8291249B2 | Method and apparatus for transitioning devices between power states based on activity request frequency | Emerging Cross-Sectional Technologies | 8 | Active |
| US8880831B2 | Method and apparatus to reduce memory read latency | Physics | 6 | Active |
| US8832485B2 | Method and apparatus for cache control | Emerging Cross-Sectional Technologies | 5 | Active |
| US7607031B2 | Power management in a communication link | Emerging Cross-Sectional Technologies | 5 | Active |
| US7366943B1 | Low-latency synchronous-mode sync buffer circuitry having programmable margin | Physics | 4 | Active |
| US8589629B2 | Method for way allocation and way locking in a cache | Emerging Cross-Sectional Technologies | 3 | Active |
| US8266389B2 | Hierarchical memory arbitration technique for disparate sources | Physics | 3 | Active |
| US8645639B2 | Hierarchical memory arbitration technique for disparate sources | Physics | 2 | Active |
| US9858221B2 | Producer/consumer remote synchronization | Physics | 2 | Active |
| US8583971B2 | Error detection in FIFO queues using signature bits | Physics | 1 | Active |
| US7657690B1 | Control of PCI memory read behavior using memory read alias and memory command reissue bits | Physics | 1 | Active |
| US7984351B2 | Data transfer device and method thereof | Physics | 1 | Active |
| US9720768B2 | System and method for early packet header verification | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.