Stacked integrated circuit package-in-package system
US7368319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Nov 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first encapsulation and a second integrated circuit package having a second encapsulation, stacking the first integrated package below the second integrated circuit package with the first encapsulation attached to the second encapsulation, forming a substrate having an opening from a substrate top surface to a substrate bottom surface, mounting the first integrated circuit package over the substrate top surface, electrically connecting the first integrated circuit package and the substrate bottom surface through the opening, and electrically connecting the second integrated circuit package and the substrate top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.