Patent · US Active

Memory cell arrays and methods for producing memory cell arrays

US7368350B2 · kind B2 · utility

1Cited by

4References

50Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dominik Olligs · Dresden, DE
Torsten Mueller · Zirndorf, DE
Karl-Heinz Kuesters · Munich, DE
Veronika Polei · Dresden, DE
Thomas Mikolajick · Birkenfeld, DE
Josef Willer · Riemerling, DE

Key dates

Filing date	Dec 20, 2005
Grant date	May 6, 2008
Priority date	—
Expiry date	Jun 28, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH10B43/30
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.