Method and apparatus for inspecting semiconductor device
US7368713B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2611
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for inspecting a wafer during a semiconductor device fabrication process. The apparatus performs, only via observation from the wafer's top surface, inspection and quantitative evaluation of a portion that is in the shadow of an incident electron beam and a buried structure in the wafer. To this end, the electron beam is emitted so that it partially penetrates a wafer surface and reaches an unexposed pattern portion to the beam. When a stereoscopic structure is constructed from the scan image based on a secondarily generated signal, generate a stereoscopic model of a pattern being tested. The secondary signal is used to detect position information of a pattern edge(s) and signal intensity. Then, use the information to calculate more than one feature quantity of the test pattern. From the calculated feature quantities, the stereoscopic structure is constructed for displaying a 3D structure of the pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.