Nonvolatile memory having latching sense amplifier and method of operation
US7369450B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharging a selected bitline to a first predetermined voltage in response to a first precharge signal. The current-to-voltage converter has a current input coupled to the selected bitline, and a voltage output. A latch circuit has a storage node coupled to the voltage output of the current-to-voltage converter. The second precharge circuit is for precharging the storage node of the latch circuit to a second predetermined voltage in response to a second precharge signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.