Compressing test responses using a compactor
US7370254B2 · kind B2 · utility
50Cited by
62References
43Claims
0Family size
Inventors
Key dates
| Filing date | Feb 13, 2004 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.