Integrated circuit testing module including data compression
US7370256B2 · kind B2 · utility
16Cited by
21References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 6, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Mar 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.