Silicon recess improvement through improved post implant resist removal and cleans
US7371691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Nov 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.