Two-cycle sensing in a two-terminal memory array having leakage current
US7372753B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2006 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Nov 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.