Method for fabricating semiconductor device having stacked-gate structure
US7375017B2 · kind B2 · utility
1Cited by
2References
9Claims
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Key dates
| Filing date | Jan 23, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.