Chip package structure
US7375435B2 · kind B2 · utility
5Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jun 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.