Integrated semiconductor memory having sense amplifiers selectively activated at different timing
US7376026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense coupling” effects upon activation of the sense amplifiers in conjunction with capacitive coupling effects between bit lines, potential changes occur on adjacent bit lines. The integrated semiconductor memory makes it possible to simulate parasitic coupling effects between adjacent bit lines in a functional test in which the first and second sense amplifiers can be activated in temporarily delayed fashion. As a result, the test severity can be improved and test time can be saved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.