Selective silicon deposition for planarized dual surface orientation integration

US7378306B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Gregory S. Spencer · Pflugerville, US
• Peter J. Beckage · Austin, US
• Mariam Sadaka · Austin, US
• Veer Dhandapani · Round Rock, US

Key dates

• Filing date: Mar 14, 2006
• Grant date: May 27, 2008
• Expiry date: May 19, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00

Abstract

A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon layer (220) with a selective silicon deposition process that covers the SOI semiconductor layer (210) with a crystalline semiconductor layer (216). By forming first gate electrodes (151) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.