Mariam Sadaka
84Patents
14h-index
57Co-inventors
87Inventor score
Filing activity: Aug 17, 2000 → Sep 25, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7575968B2 | Inverse slope isolation and dual surface orientation integration | Electricity | 516 | Active |
| US8501537B2 | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods | Electricity | 200 | Active |
| US8697493B2 | Bonding surfaces for direct bonding of semiconductor structures | Electricity | 200 | Active |
| US8716105B2 | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods | Electricity | 197 | Active |
| US6893947B2 | Advanced RF enhancement-mode FETs with improved gate properties | Electricity | 123 | Expired |
| US7226833B2 | Semiconductor device structure and method therefor | Electricity | 122 | Expired |
| US7018901B1 | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain | Electricity | 65 | Expired |
| US7282402B2 | Method of making a dual strained channel semiconductor device | Electricity | 42 | Expired |
| US7655963B2 | Semiconductor device including a lateral field-effect transistor and Schottky diode | Electricity | 29 | Active |
| US7067868B2 | Double gate device having a heterojunction source/drain and strained channel | Electricity | 28 | Expired |
| US7575975B2 | Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer | Emerging Cross-Sectional Technologies | 22 | Active |
| US7435639B2 | Dual surface SOI by lateral epitaxial overgrowth | Electricity | 20 | Active |
| US7037795B1 | Low RC product transistors in SOI semiconductor process | Electricity | 19 | Expired |
| US8461017B2 | Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region | Electricity | 19 | Active |
| US7029980B2 | Method of manufacturing SOI template layer | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7205210B2 | Semiconductor structure having strained semiconductor and method therefor | Electricity | 13 | Expired |
| US7803670B2 | Twisted dual-substrate orientation (DSO) substrates | Electricity | 13 | Active |
| US7524707B2 | Modified hybrid orientation technology | Electricity | 12 | Active |
| US6465297B1 | Method of manufacturing a semiconductor component having a capacitor | Electricity | 11 | Expired |
| US7378306B2 | Selective silicon deposition for planarized dual surface orientation integration | Electricity | 10 | Expired |
| US6368929B1 | Method of manufacturing a semiconductor component and semiconductor component thereof | Electricity | 10 | Expired |
| US7504673B2 | Semiconductor device including a lateral field-effect transistor and Schottky diode | Electricity | 10 | Active |
| US8673733B2 | Methods of transferring layers of material in 3D integration processes and related structures and devices | Electricity | 10 | Active |
| US7821067B2 | Electronic devices including a semiconductor layer | Electricity | 10 | Active |
| US7564074B2 | Semiconductor device including a lateral field-effect transistor and Schottky diode | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.