Method of programming, reading and erasing memory-diode in a memory-diode array
US7379317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2004 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Apr 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.