Method and system for performing minimization of input count during structural netlist overapproximation
US7380222B2 · kind B2 · utility
7Cited by
6References
5Claims
0Family size
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Key dates
| Filing date | Sep 13, 2005 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Dec 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.