System for delaying priority boost in a priority offset amount only after detecting of preemption event during access to critical section
US7380247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2003 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Feb 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.