Andrew Dunshea
55Patents
10h-index
45Co-inventors
74Inventor score
Filing activity: Apr 23, 2003 → Nov 10, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8037203B2 | User defined preferred DNS reference | Electricity | 57 | Active |
| US7278141B2 | System and method for adding priority change value corresponding with a lock to a thread during lock processing | Physics | 22 | Expired |
| US9262357B2 | Associating process priority with I/O queuing | Physics | 17 | Active |
| US7120753B2 | System and method for dynamically adjusting read ahead values based upon memory usage | Physics | 13 | Expired |
| US7543124B1 | Method for preventing page replacement of unreferenced read-ahead file pages | Physics | 13 | Active |
| US7721047B2 | System, method and computer program product for application-level cache-mapping awareness and reallocation requests | Physics | 12 | Active |
| US7698707B2 | Scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval | Physics | 12 | Active |
| US7360218B2 | System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval | Physics | 12 | Expired |
| US7912913B2 | Facilitating presentation and monitoring of electronic mail messages with reply by constraints | Electricity | 10 | Active |
| US7454570B2 | Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor | Physics | 10 | Expired |
| US7487503B2 | Scheduling threads in a multiprocessor computer | Physics | 9 | Active |
| US7353517B2 | System and method for CPI load balancing in SMT processors | Physics | 9 | Expired |
| US7318142B2 | System and method for dynamically adjusting read ahead values based upon memory usage | Physics | 9 | Active |
| US7962913B2 | Scheduling threads in a multiprocessor computer | Physics | 8 | Active |
| US7380247B2 | System for delaying priority boost in a priority offset amount only after detecting of preemption event during access to critical section | Physics | 7 | Expired |
| US8412907B1 | System, method and computer program product for application-level cache-mapping awareness and reallocation | Physics | 6 | Active |
| US8424078B2 | Methodology for secure application partitioning enablement | Physics | 6 | Active |
| US7080220B2 | Page replacement with a re-reference indicator | Physics | 6 | Expired |
| US8612986B2 | Computer program product for scheduling ready threads in a multiprocessor computer based on an interrupt mask flag value associated with a thread and a current processor priority register value | Physics | 5 | Active |
| US7752620B2 | Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions | Physics | 5 | Active |
| US9436537B2 | Enhanced restart of a core dumping application | Physics | 4 | Active |
| US8042115B2 | Method and system for balancing component load in an input/output stack of an operating system | Physics | 4 | Active |
| US8230430B2 | Scheduling threads in a multiprocessor computer | Physics | 4 | Active |
| US7831980B2 | Scheduling threads in a multi-processor computer | Physics | 3 | Active |
| US8145870B2 | System, method and computer program product for application-level cache-mapping awareness and reallocation | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.