Strain engineering—HDP thin film with tensile stress for FEOL and other applications
US7381451B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Feb 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
High density plasma (HDP) techniques form high tensile stress silicon oxide films. The HDP techniques use low enough temperatures to deposit high tensile stress silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve a two phase process: a HDP deposition phase, wherein silanol groups are formed in the silicon oxide film, and a bond reconstruction phase, wherein water is removed and tensile stress is induced in the silicon oxide film. Transistor strain can be generated in NMOS or PMOS devices using strategic placement of the high tensile stress silicon oxide. Example applications include high tensile stress silicon oxides for use in shallow trench isolation structures, pre-metal dielectric layer and silicon on insulator substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.