Method of forming dual interconnects in manufacturing MRAM cells

US7381574B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• Altis Semiconductor · FR

Inventors

• Woosik Kim · Suwon-si, KR
• Chanro Park · Clifton Park, US

Key dates

• Filing date: Nov 30, 2005
• Grant date: Jun 3, 2008
• Expiry date: Jul 14, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/01

Abstract

A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.