Method of forming a field effect transistor comprising a stressed channel region
US7381602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, tensile stress is created in the channel region. The tensile stress leads to an increase of the electron mobility in the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.