Strain modulation employing process techniques for CMOS technologies
US7384861B2 · kind B2 · utility
3Cited by
4References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 18, 2005 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Apr 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.