Transistor arrangement in monocrystalline substrate having stress exerting insulators
US7385256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2005 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas, and which stress them accordingly, are provided in the semiconductor substrate in addition to the active areas formed by sections of a semiconductor substrate. The insulator structures are respectively established on a base section by which a tensile stress is induced in adjacent active areas. Insulator structures respectively next to a p-type FET are selectively provided with additional buffer layers by which, due to production, a compressive stress is induced in adjacent structures. The charge carrier mobility is increased both for electrons I n the channel regions of the n-type FETs and for holes in the channel regions of the p-type FETs, and the functionality is improved both for the n-type FETs and for the p-type FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.