Repetitive erase verify technique for flash memory devices
US7385851B1 · kind B1 · utility
15Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/345
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erase verify operations as described herein can be utilized for a flash memory device having an array of memory cells. The erase verify operations employ repetitive erase verify testing to double-check previously verified bits that might otherwise relax or settle into an under-erased state. Following an initial erase verify procedure, an erase verify operation may perform a secondary erase verify procedure and apply additional erase pulses to bits that have become under-erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.