Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US7386656B2 · kind B2 · utility
139Cited by
126References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2006 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Sep 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.