Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
US7386689B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2005 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Jan 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7821
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided in which multiple PEs share their connections to multiple data bits in the memory array. Each PE is associated with a plurality of memory buffer registers, which stores data read from (or to be written to) one or two memory data bits. In horizontal (normal) mode connection the memory bits are selected so that all the bits of a given byte are stored in the same PE, i.e., each set of buffer registers associated with a respective PE contains one byte as seen by an external device. In vertical (bit serial) mode, each set of buffer registers contains the successive bits at successive locations in the memory corresponding to that PEs position in the memory word. The selection is achieved utilizing a multiplexer on the input to the register and a pair of tri-state drivers which drive each data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.