Strained finFET CMOS device structures
US7388259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2002 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Nov 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.