Patterning of doped poly-silicon gates

US7390708B2 · kind B2 · utility

Assignee

• INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW · BE

Inventors

• Marc Demand · Saint-Jean-Geest, BE
• Denis Shamiryan · Heverlee, BE
• Vasile Paraschiv · Kessel-Lo, BE

Key dates

• Filing date: Oct 22, 2007
• Grant date: Jun 24, 2008
• Expiry date: Oct 22, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32155
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.