Trench power MOSFET fabrication using inside/outside spacers

US7390717B2 · kind B2 · utility

Assignee

• International Rectifier Corporation · US

Inventors

• Jianjun Cao · Torrance, US
• Paul M. Harvey · Austin, US
• David Kent · Lake Elsinore, US
• Robert Montgomery · Cowbridge, GB
• Kyle Spring · Temecula, US

Key dates

• Filing date: Feb 9, 2005
• Grant date: Jun 24, 2008
• Expiry date: Dec 13, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.