Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US7392338B2 · kind B2 · utility
135Cited by
126References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2006 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Sep 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.