Method of fabricating a semiconductor memory device
US7393748B2 · kind B2 · utility
7Cited by
0References
17Claims
0Family size
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Key dates
| Filing date | Dec 12, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Dec 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
Abstract
A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.