Low temperature CVD process with selected stress of the CVD layer on CMOS devices

US7393765B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Hiroji Hanawa · Sunnyvale, US
• Kartik Ramaswamy · San Jose, US
• Kenneth S. Collins · San Jose, US
• Amir Al-Bayati · San Jose, US
• Biagio Gallo · Los Gatos, US
• Andrew Nguyen · San Jose, US

Key dates

• Filing date: Apr 19, 2007
• Grant date: Jul 1, 2008
• Expiry date: Apr 19, 2027

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T29/5313
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.