Protective coating for planarization
US7393789B2 · kind B2 · utility
86Cited by
74References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2005 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | May 2, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.