Inventor · Loomis, CA, US

Baosuo Zhou

36Patents
11h-index
37Co-inventors
71Inventor score

Filing activity: Sep 1, 2005 → Apr 27, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7732343B2 Simplified pitch doubling process flow Electricity 545 Active
US7393789B2 Protective coating for planarization Emerging Cross-Sectional Technologies 86 Expired
US7807575B2 Methods to reduce the critical dimension of semiconductor devices Electricity 43 Active
US9870899B2 Cobalt etch back Chemistry; Metallurgy 30 Active
US9679781B2 Methods for integrated circuit fabrication with protective coating for planarization Emerging Cross-Sectional Technologies 25 Active
US8338304B2 Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices Electricity 23 Active
US7902074B2 Simplified pitch doubling process flow Electricity 19 Active
US8852851B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same Electricity 18 Active
US8492278B2 Method of forming a plurality of spaced features Electricity 16 Active
US8980752B2 Method of forming a plurality of spaced features Electricity 14 Active
US8836083B2 Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices Electricity 11 Active
US7659208B2 Method for forming high density patterns Electricity 10 Active
US7662718B2 Trim process for critical dimension control for integrated circuits Electricity 8 Active
US10784086B2 Cobalt etch back Chemistry; Metallurgy 7 Active
US9184159B2 Simplified pitch doubling process flow Electricity 6 Active
US8324107B2 Method for forming high density patterns Electricity 6 Active
US9003651B2 Methods for integrated circuit fabrication with protective coating for planarization Emerging Cross-Sectional Technologies 5 Active
US9761457B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same Electricity 5 Active
US7910483B2 Trim process for critical dimension control for integrated circuits Electricity 5 Active
US9330934B2 Methods of forming patterns on substrates Electricity 4 Active
US10096483B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same Electricity 4 Active
US8479384B2 Methods for integrated circuit fabrication with protective coating for planarization Emerging Cross-Sectional Technologies 3 Active
US8030217B2 Simplified pitch doubling process flow Electricity 3 Active
US9570320B2 Method to etch copper barrier film Electricity 2 Active
US10607844B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.