Method of fabricating high-k dielectric layer having reduced impurity
US7396777B2 · kind B2 · utility
6Cited by
6References
32Claims
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Key dates
| Filing date | Apr 15, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Apr 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.