Semiconductor package structure for vertical mount and method
US7397120B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Mar 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.