Resistive memory device
US7397689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2006 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Aug 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.