Patent · US Active

Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods

US7398444B2 · kind B2 · utility

2Cited by

7References

24Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martin Brox · Munich, DE
Robert Kaiser · Kaufering, DE
Volker Kilian · Birkenfeld, DE
Wolfgang Anton Spirkl · Germering, DE

Key dates

Filing date	Sep 6, 2005
Grant date	Jul 8, 2008
Priority date	—
Expiry date	Jun 3, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/50012
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.