Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module
US7398449B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.