Yield optimization in router for systematic defects
US7398485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2006 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.