Method of forming a charge-trapping memory device

US7399673B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Georg Tempel · Zorneding, DE

Key dates

• Filing date: Jul 8, 2005
• Grant date: Jul 15, 2008
• Expiry date: May 11, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.