Method and apparatus for controlling congestion during integrated circuit design resynthesis
US7401313B2 · kind B2 · utility
4Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.