Physically highly secure multi-chip assembly
US7402442B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Dec 21, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53178
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.