Method for fabricating a capacitor
US7402860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Jan 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.