Intermediate semiconductor device structures
US7402908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material. A conformed metal layer is formed over the dielectric layer and into the at least one trench and a photoresist layer is formed over the metal layer. The photoresist layer may be deposited so that a photoresist material fills the at least one trench and forms a thinner coating on portions of the metal layer surrounding the at least one trench. At least a portion of the photoresist layer is selectively removed. For instance, portions of the photoresist layer surrounding the at least one trench may be removed while a portion of the photoresist layer remains therein. At least a portion of the metal layer is selectively removed, such as portions of the metal layer surrounding the at least one trench. The photoresist layer remaining in the trench may subsequently be removed. Intermediate semiconductor device structures are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.