Patent · US Active

Read latency control circuit

US7404018B2 · kind B2 · utility

9Cited by

1References

25Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Stefan Dietrich · Potsdam, DE
Thomas Hein · Hersbruck, DE
Patrick Heyne · Hersbruck, DE
Peter Schroegmeier · Birkenfeld, DE

Key dates

Filing date	May 25, 2005
Grant date	Jul 22, 2008
Priority date	—
Expiry date	Sep 1, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2272
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.