Handling cache miss in an instruction crossing a cache line boundary
US7404042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Jul 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/655
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.